// `include "mul_tc_16_16.v"
// `include "mul_tc_16_16_ref.v"
`default_nettype none

module mul_tc_16_16_tb;
parameter	TCLK = 10;

reg [15:0]  a         ;
reg [15:0]  b         ;
wire [31:0] product,p  ;

initial begin
    $dumpfile("sim/build/mul_tc_16_16_tb.vcd");
    $dumpvars(0, mul_tc_16_16_tb);
end

initial
begin
    repeat(20)
    begin
        a = {$random}%17'h10000;
        b = {$random}%17'h10000;
        # TCLK ;
    end
    $finish;
end

mul_tc_16_16_ref u_mul_tc_16_16_ref(
    .a (a ),
    .b (b ),
    .p (p )
);

mul_tc_16_16 u_mul_tc_16_16(
    .a       (a       ),
    .b       (b       ),
    .product (product )
);


endmodule
`default_nettype wire